The present invention concerns a semiconductor device and it particularly relates to a semiconductor device having an ESD (Electro-Static Discharge) protection device circuit for protecting a high voltage integrated circuit inside the semiconductor device against a high voltage.
High ESD withstanding capability has been demanded also to high voltage devices having withstanding voltage of up to about several tens of volts which are used, for example, in semiconductor integrated circuits for power sources or automobiles.
An output device at a rated current of about several amperes can absorb an ESD surge current by the device per se. Accordingly, protection against the surge current can be attained relatively easily. On the other hand, in a small output device or input device, addition of an ESD protection circuit for absorbing and suppressing the surge current is indispensable. Therefore, high ESD protection has been coped with by addition of an external device to the small output device or input device. However, this increase the cost. Accordingly, it has been demanded to incorporate an ESD protection circuit in an integrated circuit for reducing the cost.
By the way, Japanese Patent Laid-Open Publication No. 2010-205808 discloses an invention of using an IGBT (Insulated Gate Bipolar Transistor) having a usual countermeasure for latch up operation in the output stage circuit and using an IGBT in the ESD clamp circuit in which the impurity in a latch up prevention layer is lowered or the impurity concentration is eliminated and which is more tended to cause latch up operation than the output stage circuit device.
Japanese Patent Lai-Open Publication No. 2010-278188 discloses an invention in which an ESD protection circuit comprises a clamp circuit, a zener diode, a double-diffused MOSFET (DMOS), a transistor comprising IGBT, and a resistor.